Japanese Patent Application No. 2001-292128 filed on Sep. 25, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device in which nonvolatile memory devices including two charge storage regions for one word gate are arranged in an array, and a method of manufacturing the same.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon) nonvolatile semiconductor memory device is known. In such a memory device, a gate insulating layer between a channel region and a control gate is formed of a stacked film consisting of silicon oxide layers and a silicon nitride layer, and charges are trapped in the silicon nitride layer.
A device shown in FIG. 15 is known as a MONOS nonvolatile semiconductor memory device (Y. Hayashi. et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122 to 123).
In this MONOS memory cell 100, a word gate 14 is formed on a semiconductor substrate 10 with a second gate insulating layer 12 interposed therebetween. A first control gate 20 and a second control gate 30 in the shape of sidewalls are disposed on two opposing sides of the word gate 14, respectively. A first gate insulating layer 22 is present between the bottom of the first control gate 20 and the semiconductor substrate 10. An insulating layer 24 is present between the side of the first control gate 20 and the word gate 14. A first gate insulating layer 32 is present between the bottom of the second control gate 30 and the semiconductor substrate 10. An insulating layer 34 is present between the side of the second control gate 30 and the word gate 14. Impurity layers 16 and 18 which make up either a source region or a drain region are formed in the semiconductor substrate 10 between the control gate 20 and the control gate 30 which face each other in the adjacent memory cells.
As described above, one memory cell 100 includes two MONOS memory elements, one on each side of the word gate 14. These two MONOS memory elements are controlled separately. Therefore, one memory cell 100 is capable of storing two bits of information.
The present invention may provide a semiconductor device including MONOS nonvolatile memory devices, each having two charge storage regions, and a method of manufacturing the same.
One aspect of the present invention relates to a semiconductor device including a memory cell array in which nonvolatile memory devices are arranged in a matrix of a plurality of rows and columns,
wherein each of the nonvolatile memory devices comprises:
a word gate which is formed over a semiconductor layer with a second gate insulating layer interposed therebetween;
an impurity layer which is formed in the semiconductor layer and forms at least one of a source region and a drain region; and
first and second control gates in a shape of sidewalls which are formed along two opposing sides of the word gate, respectively,
wherein the first control gate is disposed over the semiconductor layer with a first gate insulating layer interposed therebetween, a first side insulating layer being interposed between the first control gate and the word gate,
wherein the second control gate is disposed over the semiconductor layer with a first gate insulating layer interposed therebetween, a first side insulating layer being interposed between the second control gate and the word gate,
wherein each of the first and second control gates extends in a first direction,
wherein the first and second control gates adjacent in a second direction, which intersects the first direction, with the impurity layer interposed therebetween are connected with a common contact section,
wherein the common contact section includes a contact conductive layer, a stopper insulating layer, and a cap insulating layer,
wherein the contact conductive layer is continuous with the first and second control gates,
wherein the stopper insulating layer is disposed outside the contact conductive layer, and
wherein the cap insulating layer is formed at least over the stopper insulating layer.
According to the semiconductor device of this aspect of the present invention, since the first and second control gates in the shape of sidewalls are connected with the common contact section, electrical connection with narrow control gates can be secured reliably.
The semiconductor device of this aspect of the present invention may have the following features.
(A) The contact conductive layer may be disposed inside the cap insulating layer with a second side insulating layer interposed therebetween. In this case, the second side insulating layer may be formed of the same material as the first side insulating layer.
(B) The contact conductive layer may be formed of the same material as the first and second control gates.
(C) An upper surface of the contact conductive layer and an upper surface of the stopper insulating layer may be formed on substantially the same level.
(D) The stopper insulating layer may be formed of a material including silicon nitride as an essential component, and the cap insulating layer may be formed of a material including silicon oxide as an essential component.
(E) An interlayer dielectric may be further provided over the cap insulating layer, the contact conductive layer may include a depression on which a contact hole is formed, the contact hole being formed through the cap insulating layer and the interlayer dielectric, and the contact hole may be filled with a plug conductive layer.
(F) The contact conductive layer may be disposed over the semiconductor layer with a contact insulating layer interposed therebetween, and the contact insulating layer may be formed of the same material as the first gate insulating layer.
(G) An upper end of the first side insulating layer may be located higher than the first and second control gates. This enables an embedding insulating layer which covers the control gates to be formed reliably. Specifically, the adjacent first and second control gates are covered with an embedding insulating layer. The embedding insulating layer is formed between the two side insulating layers facing each other which are disposed in contact with the first and second control gates.
(H) The first and second control gates adjacent to each other may be covered with an insulating layer.
(I) The common contact section may be provided adjacent to an end of the impurity layer. A plurality of the impurity layers may be arranged, and a plurality of the common contact sections may be provided alternately on one ends and opposite ends of the plurality of the impurity layers.
(J) Each of the first gate insulating layer and the first side insulating layer may be formed of a stacked film including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
Another aspect of the present invention relates to a method of manufacturing a semiconductor device including a memory cell array in which nonvolatile memory devices are arranged in a matrix of a plurality of rows and columns, the method comprising steps of:
forming a first insulating layer to be a second gate insulating layer over a semiconductor layer;
forming a first conductive layer over the first insulating layer;
forming a stopper layer over the first conductive layer;
forming a gate layer by patterning the first conductive layer and the stopper layer;
forming a first gate insulating layer at least over the semiconductor layer;
forming a first side insulating layer along two opposing sides of the gate layer;
forming a second conductive layer in a formation region of the memory cell array;
forming first and second control gates in a shape of sidewalls by forming a mask on the second conductive layer in a region corresponding to a formation region of a common contact section and anisotropically etching the second conductive layer;
forming a contact conductive layer in the formation region of the common contact section by polishing a second insulating layer and the second conductive layer by using a chemical mechanical polishing method so that the stopper layer is exposed, after forming the second insulating layer in the formation region of the memory cell array;
forming an impurity layer which forms at least one of a source region and a drain region in the semiconductor layer;
forming a mask on a third insulating layer in a region corresponding to the formation region of the common contact section after forming the third insulating layer to be a cap insulating layer in the formation region of the memory cell array, and patterning the third insulating layer, then forming the cap insulating layer in the formation region of the common contact section by; and
forming a word gate and a word line connected with the word gate by patterning the gate layer, a third conductive layer and the stopper layer after forming the third conductive layer in the formation region of the memory cell array, and forming a stopper insulating layer in the formation region of the common contact section.
According to the method of manufacturing a semiconductor device of this aspect of the present invention, since the common contact section can be formed together with the first and second control gates in the shape of sidewalls, reliable electrical connection can be secured through the common contact section.
The manufacturing method according to this aspect of the present invention may have the following features.
(a) The step of patterning the gate layer may include a step of forming the stopper insulating layer over the first conductive layer.
(b) The contact conductive layer may be formed in the same formation step as the control gates.
(c) The method may further comprise steps of forming a contact insulating layer over the semiconductor layer and forming a second side insulating layer along the contact conductive layer, in the formation region of the common contact section,
the contact insulating layer may be formed in the same step as the step of forming the first gate insulating layer, and
the second side insulating layer may be formed in the same step as the step of forming the first side insulating layer.
(d) The method may further comprise steps of:
forming an interlayer dielectric in the formation region of the memory cell array and forming a contact hole on the contact conductive layer through the cap insulating layer and the interlayer dielectric; and
filling the contact hole with a plug conductive layer.
(e) The stopper layer may be formed of a material including silicon nitride as an essential component, and
the third insulating layer may be formed of a material including silicon oxide as an essential component.
(f) Each of the first gate insulating layer and the first side insulating layer may be formed in the same formation step and may be formed of a stacked film including a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
(g) The first side insulating layer may be formed so that an upper end of the first side insulating layer is located higher than the first and second control gates.
(h) The first and second control gates adjacent to each other with the impurity layer interposed therebetween may be formed so as to be covered with an embedding insulating layer in the step of polishing the second insulating layer by using the chemical mechanical polishing method (hereinafter called xe2x80x9cCMP methodxe2x80x9d).
(i) The common contact section may be formed adjacent to an end of the impurity layer. A plurality of the impurity layers may be arranged, and a plurality of the common contact sections may be provided alternately on one ends and opposite ends of the plurality of the impurity layers.